Resistance and Capacitance Extractor.
Translates VHDL to gate-level
Schematic design editor
Layout versus schematic checker
Advanced device properties attached to devices in the extracted netlist
Minimizes power consumption at the RTL and gate level
Physical design rule checker
Physical design verification
Advanced analog design and simulation platform (addition to L tier)
Verify IC Design Layout geometry.
Library of IPs for design and verification
Schematic design editor with Verilog interface
Synthesis RTL source code.
Translates Verilog HDL to gate-level
Static timing analyzer
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