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National Scientific Facilities & Equipment

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MIMOS - IC DESIGN PLACE AND ROUTE TOOL

Netlist-to-GDSII implementation system. Netlist-to-GDSII implementation system

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MIMOS - IC DESIGN TIMING ANALYSIS TOOL

Static timing and cross talk analyzer. Static timing and cross talk analyzer

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MIMOS - IC DESIGN LAYOUT EXTRACTION

Resistance and Capacitance Extractor.

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MIMOS - IC DESIGN VHDL COMPILER TOOL

Translates VHDL to gate-level

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MIMOS - IC DESIGN SCHEMATIC EDITOR L TIER

Schematic design editor

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MIMOS - IC DESIGN LAYOUT VERSUS SCHEMATIC CHECKER XL TIER

Layout versus schematic checker

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MIMOS - IC DESIGN CALIBRE ADVANCED DEVICE PROPERTIES

Advanced device properties attached to devices in the extracted netlist

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MIMOS - IC DESIGN POWER SYNTHESIS

Minimizes power consumption at the RTL and gate level

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MIMOS - IC DESIGN RULE CHECKER XL TIER

Physical design rule checker

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MIMOS - IC DESIGN PHYSICAL VERIFICATION

Physical design verification

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MIMOS - IC DESIGN ANALOG DESIGN ENVIROMENT XL TIER

Advanced analog design and simulation platform (addition to L tier)

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MIMOS - IC DESIGN LAYOUT VERIFICATION

Verify IC Design Layout geometry.

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MIMOS - SILICON-PROVEN IP

Library of IPs for design and verification

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MIMOS - IC DESIGN SCHEMATIC VERILOG INTERFACE

Schematic design editor with Verilog interface

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MIMOS - IC DESIGN RTL SYNTHESIS

Synthesis RTL source code.


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